1. Field of the Invention
The present invention relates to data storage devices, and in particular, relates to operating methods for FLASH memories.
2. Description of the Related Art
A FLASH memory is a common non-volatile memory, which is erased and programmed electrically. In common embodiments, the storage cells of a FLASH memory are implemented by NAND gates.
A storage cell operated by a read/write circuit of a FLASH memory may just correspond to a single bit (i.e., an SLC, abbreviated from a Single-Level Cell) or correspond to multiple bits (i.e., an MLC, abbreviated from a Multi-Level Cell). FIG. 1A shows the probability distribution of the different states of an SLC, along a voltage axis. FIG. 1B shows the probability distribution of the different states of an MLC, along a voltage axis.
Referring to FIG. 1A, for an SLC, a voltage reference Vref_SLC is adopted to recognize a value ‘0’ and value ‘1’.
Referring to FIG. 1B, for an MLC, the different two-bit values ‘00’, ‘01’, ‘10’ and ‘11’ are represented by different voltage intervals. Two stages are required for programming a storage cell into a multi-level cell. The first stage is named a strong page stage. The second stage is named a weak page stage. By the strong page stage, a storage cell is transformed to represent a single binary value. By the weak page stage, a strong paged storage cell is further transformed to represent a two-bit value. FIG. 1C shows the probability distribution of the different states of a strong paged storage cell, along a voltage axis. A voltage reference Vref_MLC_SP is adopted to recognize a strong-paged value ‘0’ and a strong-paged value ‘1’. Note that the voltage reference Vref_MLC_SP is different from the voltage reference Vref_SLC.
In summary, the voltage reference adopted in the data recognition of a storage cell depends on the write operation of the storage cell. To accurately read a storage cell, the voltage reference Vref_SLC is adopted when the storage cell was programmed to be a single level cell. Otherwise, when the storage cell was programmed via the strong page stage for a multi-level cell, the voltage reference Vref_MLC_SP is adopted. However, when a power failure event or a reset process occurs, the mapping between the read and write operations may be disrupted. Accordingly, operation errors may occur.